Semiconductor memories include memory cells that store data. The data is stored by writing the data to the memory cells. The data may be retrieved by reading the memory cells. The stored data should be accurately written to the memory cells, otherwise, the data will not be accurate when read. In some memories, data is written by repeating a programming cycle until the correct data is in fact stored by the memory cells. In determining the necessary number of programming cycles, the data currently stored by the memory cells being written may be read and compared to the expected write data in order to determine if additional programming cycles need to be performed. No further programming cycles are necessary when it is determined that an acceptable number of memory cells have accurately stored the expected write data.
In some memories, the number of memory cells that may require additional programming may be determined by using a comparator to compare a current that represents a number of memory cells that do not yet accurately store the expected write data (which are referred to hereinafter as “failing memory cells”) to a reference current. The reference current represents a reference number of memory cells. Each of the failing memory cells contributes an incremental current to the total current. The total current is compared to the reference current. By comparing the two currents, the number of failing memory cells can be determined relative to the reference number of memory cells. Based on the comparison of the currents, for example, whether the current representing the number of failing memory cells is greater than the reference current, it can de determined whether the number of failing memory cells is greater than the reference number of memory cells.
The current comparison is repeated after a programming cycle to gauge whether additional programming cycles are necessary. The comparison takes time, however, because it takes time to develop and compare the current representing the number of failing memory cells to the reference current. A contributing factor to this time is the electrical load presented to the comparator. A higher electrical load typically results in longer times to complete the comparison. As the number of memory cells being evaluated during a comparison increases, such as with higher density memories, the electrical load presented during comparison also increases. As a result, the time for the comparison to complete increases, thereby slowing down the overall operation.